Verilog串口UART程序
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if (!rx_busy !rx_d2) begin
rx_busy = 1;
rx_sample_cnt = 1;
rx_cnt = 0;
end
// Start of frame detected, Proceed with rest of data
if (rx_busy) begin
rx_sample_cnt = rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) (rx_cnt == 0)) begin
rx_busy = 0;
end else begin
rx_cnt = rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 rx_cnt 9) begin
rx_reg[rx_cnt - 1] = rx_d2;
end
if (rx_cnt == 9) begin
rx_busy = 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err = 1;
end else begin
rx_empty = 0;
rx_frame_err = 0;
// Check if last rx data was not unloaded,
rx_over_run = (rx_empty) ? 0 : 1;
end
end
end
end
end
end
if (!rx_enable) begin
rx_busy = 0;
end
end
// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg = 0;
tx_empty = 1;
tx_over_run = 0;
tx_out = 1;
tx_cnt = 0;
end else begin
if (ld_tx_data) begin
if (!tx_empty) begin
tx_over_run = 0;
end else begin
tx_reg = tx_data;
tx_empty = 0;
end
end
if (tx_enable !tx_empty) begin
tx_cnt = tx_cnt + 1;
if (tx_cnt == 0) begin
tx_out = 0;
end
if (tx_cnt > 0 tx_cnt 9) begin
tx_out = tx_reg[tx_cnt -1];
end
if (tx_cnt == 9) begin
tx_out = 1;
tx_cnt = 0;
tx_empty = 1;
end
end
if (!tx_enable) begin
tx_cnt = 0;
end
end
endmodule本文引用地址：http://www.104case.com/article/149350.htm
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