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        S5PV210(TQ210)學習筆記——Nand驅動之HWECC
        
						
        
				作者：
				時間：2016-11-28
				來源：網絡

							
				
				
				
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			前幾天匆忙間發了一篇關于S5PV210的8位HWECC驅動的文章，但是后來發現存在嚴重的Bug，就將原來那篇文章刪除了，這里先說聲抱歉，但是，HWECC能有效的節省CPU占用量，我仔細調試了S5PV210的HWECC部分，現在剛調好1位的HWECC，為了表示誤發原來那篇文章的歉意，現在將代碼放在這里，與大家分享：
        1. #include
        2. #include
        3. #include
        4. #include
        5. #include
        6. #include
        7. #include
        8. #include
        10. #defineNFCONT_MECCLOCK(1<<7)
        11. #defineNFCONT_SECCLOCK(1<<6)
        12. #defineNFCONT_INITMECC(1<<5)
        13. #defineNFCONT_INITSECC(1<<4)
        14. #defineNFCONT_INITECC(NFCONT_INITMECC|NFCONT_INITSECC)
        16. structs5p_nand_regs{
        17. unsignedlongnfconf;
        18. unsignedlongnfcont;
        19. unsignedlongnfcmmd;
        20. unsignedlongnfaddr;
        21. unsignedlongnfdata;
        22. unsignedlongnfmeccd0;
        23. unsignedlongnfmeccd1;
        24. unsignedlongnfseccd;
        25. unsignedlongnfsblk;
        26. unsignedlongnfeblk;
        27. unsignedlongnfstat;
        28. unsignedlongnfeccerr0;
        29. unsignedlongnfeccerr1;
        30. unsignedlongnfmecc0;
        31. unsignedlongnfmecc1;
        32. unsignedlongnfsecc;
        33. unsignedlongnfmlcbitpt;
        34. };
        36. staticvolatilestructs5p_nand_regs*s5p_nand_regs;
        37. staticstructnand_chip*nand_chip;
        38. staticstructmtd_info*s5p_mtd_info;
        39. staticstructclk*s5p_nand_clk;
        40. staticinteccmode;
        42. staticstructnand_ecclayouts5p_nand_oob_64={
        43. .eccbytes=16,
        44. .eccpos={
        45. 40,41,42,43,44,45,46,47,
        46. 48,49,50,51,52,53,54,55
        47. },
        48. .oobfree={
        49. {
        50. .offset=2,
        51. .length=38
        52. }
        53. }
        54. };
        56. staticstructmtd_partitions5p_nand_partions[]={
        57. [0]={
        58. .name="bootloader",
        59. .offset=0,
        60. .size=SZ_1M,
        61. },
        63. [1]={
        64. .name="kernel",
        65. .offset=MTDPART_OFS_APPEND,
        66. .size=5*SZ_1M,
        67. },
        69. [2]={
        70. .name="rootfs",
        71. .offset=MTDPART_OFS_APPEND,
        72. .size=MTDPART_SIZ_FULL,
        73. },
        74. };
        76. staticvoids5p_nand_cmd_ctrl(structmtd_info*mtd,intcmd,unsignedintctrl)
        77. {
        78. if(ctrl&NAND_CTRL_CHANGE){
        79. if(ctrl&NAND_NCE){
        80. if(cmd!=NAND_CMD_NONE){
        81. s5p_nand_regs->nfcont&=~(1<<1);
        82. }
        83. }else{
        84. s5p_nand_regs->nfcont|=(1<<1);
        85. }
        86. }
        88. if(cmd!=NAND_CMD_NONE){
        89. if(ctrl&NAND_CLE)
        90. s5p_nand_regs->nfcmmd=cmd;
        91. elseif(ctrl&NAND_ALE)
        92. s5p_nand_regs->nfaddr=cmd;
        93. }
        94. }
        96. staticints5p_nand_ready(structmtd_info*mtd){
        97. return(s5p_nand_regs->nfstat&0x1);
        98. }
        100. staticvoids5p_ecc_hwctl(structmtd_info*mtd,intmode){
        102. eccmode=mode;
        104. s5p_nand_regs->nfconf&=~(0x3<<23);
        106. /*InitmainECC&unlock*/
        107. s5p_nand_regs->nfcont|=NFCONT_INITMECC;
        108. s5p_nand_regs->nfcont&=~NFCONT_MECCLOCK;
        109. }
        111. staticints5p_ecc_calculate(structmtd_info*mtd,constuint8_t*dat,
        112. uint8_t*ecc_code){
        114. unsignedlongnfmecc0=s5p_nand_regs->nfmecc0;
        116. /*Lock*/
        117. s5p_nand_regs->nfcont|=NFCONT_MECCLOCK;
        119. ecc_code[0]=(nfmecc0)&0xff;
        120. ecc_code[1]=(nfmecc0>>8)&0xff;
        121. ecc_code[2]=(nfmecc0>>16)&0xff;
        122. ecc_code[3]=(nfmecc0>>24)&0xff;
        124. return0;
        125. }
        127. staticints5p_ecc_correct(structmtd_info*mtd,uint8_t*dat,uint8_t*read_ecc,uint8_t*calc_ecc){
        128. unsignednfmeccd0,nfmeccd1;
        129. unsignedlongnfeccerr0;
        131. nfmeccd0=(read_ecc[1]<<16)|read_ecc[0];
        132. nfmeccd1=(read_ecc[3]<<16)|read_ecc[2];
        134. s5p_nand_regs->nfmeccd0=nfmeccd0;
        135. s5p_nand_regs->nfmeccd1=nfmeccd1;
        137. nfeccerr0=s5p_nand_regs->nfeccerr0;
        139. switch(nfeccerr0&0x3){
        140. case0:
        141. return0;
        142. case1:
        143. printk("s5p-nand:detectedonebiterror");
        144. dat[(nfeccerr0>>7)&0x7ff]^=1<<((nfeccerr0>>4)&0x3);
        145. return1;
        146. case2:
        147. case3:
        148. printk("s5p-nand:detecteduncorrectederror");
        149. return3;
        151. default:
        152. return-EIO;
        153. }
        154. }
        156. staticints5p_nand_read_page(structmtd_info*mtd,structnand_chip*chip,
        157. uint8_t*buf,intoob_required,intpage)
        158. {
        159. inti,stat,eccsize=chip->ecc.size;
        160. inteccbytes=chip->ecc.bytes;
        161. inteccsteps=chip->ecc.steps;
        162. intsecc_start=mtd->oobsize-eccbytes;
        163. intcol=0;
        164. uint8_t*p=buf;
        165. uint32_t*mecc_pos=chip->ecc.layout->eccpos;
        166. uint8_t*ecc_calc=chip->buffers->ecccalc;
        168. col=mtd->writesize;
        169. chip->cmdfunc(mtd,NAND_CMD_RNDOUT,col,-1);
        171. /*sparearea*/
        172. chip->ecc.hwctl(mtd,NAND_ECC_READ);
        173. chip->read_buf(mtd,chip->oob_poi,secc_start);
        174. chip->ecc.calculate(mtd,p,&ecc_calc[chip->ecc.total]);
        175. chip->read_buf(mtd,chip->oob_poi+secc_start,eccbytes);
        177. col=0;
        179. /*mainarea*/
        180. for(i=0;eccsteps;eccsteps--,i+=eccbytes,p+=eccsize){
        181. chip->cmdfunc(mtd,NAND_CMD_RNDOUT,col,-1);
        182. chip->ecc.hwctl(mtd,NAND_ECC_READ);
        183. chip->read_buf(mtd,p,eccsize);
        184. chip->ecc.calculate(mtd,p,&ecc_calc[i]);
        186. stat=chip->ecc.correct(mtd,p,chip->oob_poi+mecc_pos[0]+
        187. ((chip->ecc.steps-eccsteps)*eccbytes),0);
        188. if(stat==-1)
        189. mtd->ecc_stats.failed++;
        191. col=eccsize*(chip->ecc.steps+1-eccsteps);
        192. }
        194. return0;
        195. }
        197. staticints5p_nand_write_page(structmtd_info*mtd,structnand_chip*chip,
        198. constuint8_t*buf,intoob_required)
        199. {
        200. inti,eccsize=chip->ecc.size;
        201. inteccbytes=chip->ecc.bytes;
        202. inteccsteps=chip->ecc.steps;
        203. intsecc_start=mtd->oobsize-eccbytes;
        204. uint8_t*ecc_calc=chip->buffers->ecccalc;
        205. constuint8_t*p=buf;
        207. uint32_t*eccpos=chip->ecc.layout->eccpos;
        209. /*mainarea*/
        210. for(i=0;eccsteps;eccsteps--,i+=eccbytes,p+=eccsize){
        211. chip->ecc.hwctl(mtd,NAND_ECC_WRITE);
        212. chip->write_buf(mtd,p,eccsize);
        213. chip->ecc.calculate(mtd,p,&ecc_calc[i]);
        214. }
        216. for(i=0;iecc.total;i++)
        217. chip->oob_poi[eccpos[i]]=ecc_calc[i];
        219. /*sparearea*/
        220. chip->ecc.hwctl(mtd,NAND_ECC_WRITE);
        221. chip->write_buf(mtd,chip->oob_poi,secc_start);
        222. chip->ecc.calculate(mtd,p,&ecc_calc[chip->ecc.total]);
        224. for(i=0;i
        225. chip->oob_poi[secc_start+i]=ecc_calc[chip->ecc.total+i];
        227. chip->write_buf(mtd,chip->oob_poi+secc_start,eccbytes);
        229. return0;
        230. }
        232. staticints5p_nand_read_oob(structmtd_info*mtd,structnand_chip*chip,
        233. intpage)
        234. {
        235. uint8_t*ecc_calc=chip->buffers->ecccalc;
        236. inteccbytes=chip->ecc.bytes;
        237. intsecc_start=mtd->oobsize-eccbytes;
        239. chip->cmdfunc(mtd,NAND_CMD_READOOB,0,page);
        240. chip->ecc.hwctl(mtd,NAND_ECC_READ);
        241. chip->read_buf(mtd,chip->oob_poi,secc_start);
        242. chip->ecc.calculate(mtd,0,&ecc_calc[chip->ecc.total]);
        243. chip->read_buf(mtd,chip->oob_poi+secc_start,eccbytes);
        245. return0;
        246. }
        248. staticints5p_nand_write_oob(structmtd_info*mtd,structnand_chip*chip,
        249. intpage)
        250. {
        251. intstatus=0;
        252. inteccbytes=chip->ecc.bytes;
        253. intsecc_start=mtd->oobsize-eccbytes;
        254. uint8_t*ecc_calc=chip->buffers->ecccalc;
        255. inti;
        257. chip->cmdfunc(mtd,NAND_CMD_SEQIN,mtd->writesize,page);
        259. /*sparearea*/
        260. chip->ecc.hwctl(mtd,NAND_ECC_WRITE);
        261. chip->write_buf(mtd,chip->oob_poi,secc_start);
        262. chip->ecc.calculate(mtd,0,&ecc_calc[chip->ecc.total]);
        264. for(i=0;i
        265. chip->oob_poi[secc_start+i]=ecc_calc[chip->ecc.total+i];
        267. chip->write_buf(mtd,chip->oob_poi+secc_start,eccbytes);
        269. /*SendcommandtoprogramtheOOBdata*/
        270. chip->cmdfunc(mtd,NAND_CMD_PAGEPROG,-1,-1);
        272. status=chip->waitfunc(mtd,chip);
        274. returnstatus&NAND_STATUS_FAIL?-EIO:0;
        275. }
        278. staticints5p_nand_probe(structplatform_device*pdev){
        279. intret=0;
        280. structresource*mem;
        281. //硬件部分初始化
        282. mem=platform_get_resource(pdev,IORESOURCE_MEM,0);
        283. if(!mem){
        284. dev_err(&pdev->dev,"cantgetI/Oresourcemem");
        285. return-ENXIO;
        286. }
        288. s5p_nand_regs=(volatilestructs5p_nand_regs*)ioremap(mem->start,resource_size(mem));
        289. if(s5p_nand_regs==NULL){
        290. dev_err(&pdev->dev,"ioremapfailed");
        291. ret=-EIO;
        292. gotoerr_exit;
        293. }
        295. s5p_nand_clk=clk_get(&pdev->dev,"nand");
        296. if(s5p_nand_clk==NULL){
        297. dev_dbg(&pdev->dev,"getclkfailed");
        298. ret=-ENODEV;
        299. gotoerr_iounmap;
        300. }
        302. clk_enable(s5p_nand_clk);
        304. //s5p_nand_regs->nfconf&=~(0xfff<<4);
        305. //s5p_nand_regs->nfconf|=(3<<12)|(5<<8)|(3<<4);
        306. //s5p_nand_regs->nfcont|=3;
        308. //分配驅動相關結構體
        309. nand_chip=(structnand_chip*)kzalloc(sizeof(structnand_chip),GFP_KERNEL);
        310. if(nand_chip==NULL){
        311. dev_err(&pdev->dev,"failedtoallocatenand_chipstructure");
        312. ret=-ENOMEM;
        313. gotoerr_clk_put;
        314. }
        316. s5p_mtd_info=(structmtd_info*)kzalloc(sizeof(structmtd_info),GFP_KERNEL);
        317. if(s5p_mtd_info==NULL){
        318. dev_err(&pdev->dev,"failedtoallocatemtd_infostructure");
        319. ret=-ENOMEM;
        320. gotoerr_free_chip;
        321. }
        323. //設置驅動相關結構體
        324. nand_chip->IO_ADDR_R=(unsignedchar*)&s5p_nand_regs->nfdata;
        325. nand_chip->IO_ADDR_W=(unsignedchar*)&s5p_nand_regs->nfdata;
        327. nand_chip->cmd_ctrl=s5p_nand_cmd_ctrl;
        328. nand_chip->dev_ready=s5p_nand_ready;
        330. nand_chip->ecc.mode=NAND_ECC_HW;
        331. nand_chip->ecc.hwctl=s5p_ecc_hwctl;
        332. nand_chip->ecc.calculate=s5p_ecc_calculate;
        333. nand_chip->ecc.correct=s5p_ecc_correct;
        335. nand_chip->ecc.read_oob=s5p_nand_read_oob;
        336. nand_chip->ecc.write_oob=s5p_nand_write_oob;
        337. nand_chip->ecc.read_page=s5p_nand_read_page;
        338. nand_chip->ecc.write_page=s5p_nand_write_page;
        339. nand_chip->ecc.size=512;
        340. nand_chip->ecc.bytes=4;
        341. nand_chip->ecc.strength=1;
        342. nand_chip->ecc.layout=&s5p_nand_oob_64;
        344. s5p_mtd_info->priv=nand_chip;
        345. s5p_mtd_info->owner=THIS_MODULE;
        347. //掃描Nandflash設備
        348. if(nand_scan(s5p_mtd_info,1)){
        349. dev_dbg(&pdev->dev,"nandscanerror");
        350. gotoerr_free_info;
        351. }
        353. //添加分區信息
        354. ret=mtd_device_parse_register(s5p_mtd_info,NULL,NULL,s5p_nand_partions,ARRAY_SIZE(s5p_nand_partions));
        355. if(!ret)
        356. return0;
        358. err_free_info:
        359. kfree(s5p_mtd_info);
        360. err_free_chip:
        361. kfree(nand_chip);
        362. err_clk_put:
        363. clk_disable(s5p_nand_clk);
        364. clk_put(s5p_nand_clk);
        365. err_iounmap:
        366. iounmap(s5p_nand_regs);
        367. err_exit:
        368. returnret;
        369. }
        371. staticints5p_nand_remove(structplatform_device*pdev){
        372. nand_release(s5p_mtd_info);
        373. kfree(s5p_mtd_info);
        374. kfree(nand_chip);
        376. clk_disable(s5p_nand_clk);
        377. clk_put(s5p_nand_clk);
        379. iounmap(s5p_nand_regs);
        380. return0;
        381. }
        383. staticstructplatform_drivers5p_nand_drv={
        384. .driver={
        385. .owner=THIS_MODULE,
        386. .name="s5p-nand",
        387. },
        388. .probe=s5p_nand_probe,
        389. .remove=s5p_nand_remove,
        390. };
        392. module_platform_driver(s5p_nand_drv);
        393. MODULE_LICENSE("GPL");
        本文引用地址：http://www.104case.com/article/201611/322813.htm
        接下來的幾天我會繼續調試一下8位HWECC，不知道能不能調好，從天嵌技術支持那里獲悉，天嵌技術人員當時也調試過8位HWECC，他們從三星的某個資料中發現S5PV210的HWECC模塊只能使用1位HWECC，不知道是不是真的，我要自己來驗證一下。
        如果有什么問題歡迎留言討論，轉載原來那篇HWECC文章的朋友請自己修正一下吧。
        
				
            
                
			
							
        
                
			              
              
            
        
		
        
		
        
		
        
		
        
		
        
			
          
				
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