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        Cypress CY8CKIT-025分辨率0.1度C溫度測量解決方案

        作者: 時間:2012-10-22 來源:網絡 收藏

        公司的-025 PSoC® 精密模擬傳感器擴展板套件(EBK)包括5個傳感器,能方便快速和控制,溫度達到度C.-025 EBK設計和-030 PSoC 3開發板或CY8CKIT- PSoC開發板 一起使用,提供完整的單片溫度檢測和控制.本文介紹了PSoC®5: CY8C52系列產品主要特性,功能框圖,ARM Cortex-M3框圖以及CY8CKIT-025 PSoC® 精密模擬溫度傳感器擴展板套件(EBK)主要特性,電路圖,材料清單和PCB元件布局圖.

        本文引用地址:http://www.104case.com/article/148319.htm

        With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

        CY8C52主要特性:

        32-bit ARM Cortex-M3 CPU core

        DC to 40 MHz operation

        Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention and multiple security features

        Up to 64 KB SRAM memory

        128 bytes of cache memory

        2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 million cycles, and 20 years retention

        24-channel direct memory access (DMA) with multilayer AMBA high-performance bus (AHB) bus access

        • Programmable chained descriptors and priorities

        • High bandwidth 32-bit transfer support

        Low voltage, ultra low power

        Operating voltage range: 2.7 V to 5.5 V

        6 mA at 6 MHz

        Low power modes including:

        • 2-μA sleep mode

        • 300-nA hibernate mode with RAM retention

        Versatile I/O system

        46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs))

        Any GPIO to any digital or analog peripheral routability

        LCD direct drive from any GPIO, up to 46 × 16 segments

        CapSense® support from any GPIO

        1.2 V to 5.5 V I/O interface voltages, up to four domains

        Maskable, independent IRQ on any pin or port

        Schmitt trigger transistor-transistor logic (TTL) inputs

        All GPIOs configurable as open drain high/low, pull up/down, High-Z, or strong output

        25 mA sink on SIO

        Digital peripherals

        20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs)

        Full-Speed (FS) USB 2.2 Mbps using a 24 MHz external oscillator

        Four 16-bit configurable timer, counter, and PWM blocks

        Library of standard peripherals

        • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

        • SPI, UART, and I2C

        • Many others available in catalog

        Library of advanced peripherals

        • Cyclic redundancy check (CRC)

        • Pseudo random sequence (PRS) generator

        • Local interconnect network (LIN) bus 2.0

        • Quadrature decoder

        Analog peripherals (2.7 V VDDA 5.5 V)

        1.024 V ±1% internal voltage reference

        Successive approximation register (SAR) analog-to-digital converter (ADC), 12-bit at 700 ksps

        One 8-bit, 5.5-Msps current DAC (IDAC) or 1-Msps voltage DAC (VDAC)

        Two comparators with 95-ns response time

        CapSense support

        Programming, debug, and trace

        Serial wire debug (SWD) and single-wire viewer (SWV) interfaces

        Cortex-M3 flash patch and breakpoint (FPB) block

        Cortex-M3 data watchpoint and trace (DWT) generates data trace information

        Cortex-M3 Instrumentation Trace Macrocell (ITM) can be used for printf-style debugging

        DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface

        Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces

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